SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3017/S3018
(TA = -40°C to +85°C, VCC = 5 V ±5%)
Table 2. S3017 AC Timing Characteristics
Symbol
Description
Min
Typ
Max
Units
tDPICLK
PICLK Delay from PCLK
0
5.5
ns
tSPIN
tHPIN
PIN [7:0] Set-up Time w.r.t. PICLK
PIN [7:0] Hold Time w.r.t. PICLK
1.5
1
ns
ns
tDSER
Serial Clock (LPDATOP) Low to SERDATOP/N
Valid Prop Delay
0
500
60
ps
%
Serial Clock (LPDATOP) Duty Cycle
40
tDRP
REFCKINP High to PCLK High Valid Prop Delay
7.0
11.0
ns
Figure 9. PIN AC Input Timing
PCLK
tD
PICLK
PICLK
tS
tH
PIN
PIN
PIN[7:0]
Notes on TTL Output Timing:
1. When a set-up time is specified on TTL signals between an input and a clock, the set-
up time is the time in nanoseconds from the 50% point of the input to the 50% point of
the clock.
2. When a hold time is specified on TTL signals between an input and a clock, the hold time
is the time in nanoseconds from the 50% point of the clock to the 50% point of the input.
Figure 10a. Clock and Data Output
Timing with TSCLKSEL Asserted
Figure 10b. REFCKIP High to PCLK
High Valid Prop Delay
REFCKINP
LPDATOP
tD
tD
SER
RP
SERDATOP/N
PCLK
Notes on PECL Output Timing:
1. Output propagation delay time of high speed
PECL outputs is the time in nanoseconds from the
cross-over point of the reference signal to the cross-
over point of the output.
17
December 10, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
