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S3017A/H1 参数 Datasheet PDF下载

S3017A/H1图片预览
型号: S3017A/H1
PDF下载: 下载PDF文件 查看货源
内容描述: [Transmitter, 1-Func, PQFP52, PLASTIC, QFP-52]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 22 页 / 147 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER  
S3017/S3018  
S3018 Pin Assignment and Descriptions (Continued)  
Pin Name  
Level I/O  
Pin # Description  
REFSEL  
TTL  
I
7
Reference select used to select the reference clock frequency.  
Set low to select 77.76 MHz. Set high to select 19.44 MHz for  
applications less demanding than SONET/SDH.  
CAP1  
CAP2  
I
1
52  
The loop filter capacitor is connected to these pins. The  
capacitor value should be 0.1µf ±10% tolerance, X7'R dielectric.  
50V is recommended (16V is acceptable).  
POUT7  
POUT6  
POUT5  
POUT4  
POUT3  
POUT2  
POUT1  
POUT0  
TTL  
TTL  
O
O
30  
29  
23  
22  
20  
19  
16  
12  
Parallel data bus, a 77.76 Mbyte/sec word, aligned to the  
POCLK parallel output clock. POUT7 is the most significant bit  
(corresponding to bit 1 of each PCM word, the first bit received).  
POUT0 is the least significant bit (corresponding to bit 8 of each  
PCM word, the last bit received). POUT(7-0) is updated on the  
falling edge of POCLK.  
FP  
11  
Frame pulse. Indicates frame boundaries in the incoming data  
stream (SERDATI). If framing pattern detection is enabled, as  
controlled by the OOF input, FP pulses high for one POCLK  
cycle when a 48-bit sequence matching the framing pattern is  
detected on the serial data inputs. When framing pattern  
detection is disabled, FP pulses high when the incoming data  
stream, after byte alignment, matches the framing pattern. FP is  
updated on the falling edge of POCLK.  
POCLK  
TTL  
TTL  
O
O
9
Parallel output clock, a 77.76 MHz nominally 50% duty cycle,  
byte rate output clock, that is aligned to POUT(7-0) byte serial  
output data. POUT(7-0) and FP are updated on the falling edge  
of POCLK.  
LOCKDET  
35  
Clock recovery indicator. Set high when the internal clock  
recovery has locked onto the incoming data stream. LOCKDET  
is an asynchronous output.  
AVEE  
0V  
+5V  
+5V  
0V  
2, 39, 41, Analog 0V  
43  
AVCC  
3, 38, 40, Analog +5V  
47  
ECLVCC  
ECLVEE  
5, 15, 25, Digital +5V  
28, 37, 50  
6, 10, 18, Digital 0V  
21, 32, 36  
TTLGND  
TTLVCC  
NC  
0V  
+5V  
13, 17, 27 Digital 0V  
14, 24, 26 Digital +5V  
51  
No Connection  
11  
December 10, 1999 / Revision B