S2204
QUAD GIGABIT ETHERNET DEVICE
Table 17. S2204 Receiver Timing (Full and Half Clock Mode)
Parameters
Description
Data Setup w.r.t. RBC1/0x
Data Hold w.r.t. RBC1/0x
Data Setup w.r.t. RBC1/0x
Min
2.5
2.5
2.5
Max Units Conditions
at 1.25 Gbps 1,2
TMODE = 1
T3
T4
T5
ns
ns
ns
TMODE = 1
at 1.25 Gbps 1,2
TMODE = 1
T6
T7
Data Hold w.r.t. RBC1/0x
Time from RBC1x rise to RBC0x rise
RBC1x Rise and Fall Times
RBC0x Rise and Fall Times
DOUTx Rise and Fall Times
RBC1/0x Duty Cycle
2.5
7.5
ns
ns
ns
ns
ns
%
TMODE = 1
8.5
2.4
2.4
2.4
60
at 1.25 Gbps 1,2
TR1, TF1
TR0, TF0
TDR, TDF
Duty Cycle
See note 2. See Figure 20.
See note 2. See Figure 20.
See note 2. See Figure 19.
See note 1.
40
1. Measurements made from the reference voltage levels of the clock (1.4V) to the valid input or output data levels (.8V or 2.0V).
2. TTL/CMOS AC timing measurements are assumed to have an output load of 10pf.
Table 18. S2204 Receiver Timing (External Clock Mode)
Parameters
Description
Min
Max Units
Conditions
10 pf load capacitance at the
end of a 3 inch 50 Ω
transmission line.
TBCA to DOUTx
Propagation Delay
T8
3.0
8.0
ns
1. Measurements made from the reference voltage levels of the clock (1.4V) to the valid input or output data levels (.8V
or 2.0V).
26
October 9, 2000 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
