QUAD GIGABIT ETHERNET DEVICE
S2204
Figure 13. Transmitter Timing (REFCLK Mode, TMODE = 0)
REFCLK
DINx[0:9]
T1
T2
SERIAL DATA OUT
Table 15. S2204 Transmitter Timing (REFCLK Mode, TMODE = 0)
Parameters
Description
Data Setup w.r.t. REFCLK
Data Hold w.r.t. REFCLK
Min
0.5
1.5
Max Units
Conditions
See Note 1.
T1
T2
-
-
ns
ns
1. All AC measurements are made from the reference voltage levels of the clock (1.4V) to the valid input or output data
levels (.8V or 2.0V).
Figure 14. Transmitter Timing (TBC Mode, TMODE = 1)
TBCx
DINx[0:9]
T1
T2
SERIAL DATA OUT
Table 16. S2204 Transmitter Timing (TBC Mode, TMODE = 1)
Parameters
Description
Data Setup w.r.t. TBC
Data Hold w.r.t. TBC
Min
1.0
0.5
Max Units
Conditions
See Note 1.
T1
T2
-
-
ns
ns
Phase drift between TBCx and
REFCLK
-3
+3
ns
1. All AC measurements are made from the reference voltage levels of the clock (1.4V) to the valid input or output data
levels (.8V or 2.0V).
25
October 9, 2000 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
