S2204
QUAD GIGABIT ETHERNET DEVICE
Table 10. Receiver Output Pin Assignment and Descriptions (Continued)
Pin Name
Level
I/O
Pin #
Description
RBC1C
RBC0C
TTL
O
U5
U4
Receive Byte Clocks. Parallel receive data, DOUTC[0:9] and
COM_DETC are valid on the rising edge of RBC1C when in full
clock mode and valid on the rising edge of both RBC1C and
RBC0C in half clock mode.
DOUTD9
DOUTD8
DOUTD7
DOUTD6
DOUTD5
DOUTD4
DOUTD3
DOUTD2
DOUTD1
DOUTD0
TTL
O
T6
T7
Channel D Receiver Data Outputs. Parallel data on this bus is
valid on the rising edge of RBC1D in full clock mode and valid on
the rising edge of both RBC1D and RBC0D in half clock mode.
U11
R10
U9
R9
T9
U8
U7
T8
COM_DETD
TTL
TTL
O
O
U6
Channel D Comma Detect. A High on this output indicates that a
valid K28.5 has been detected and is present on the parallel data
outputs DOUTD[0:9].
RBC1D
RBC0D
T10
U10
Receive Byte Clocks. Parallel receive data, DOUTD[0:9] and
COM_DETD are valid on the rising edge of RBC1D when in full
clock mode and valid on the rising edge of both RBC1D and
RBC0D in half clock mode.
18
October 9, 2000 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
