欢迎访问ic37.com |
会员登录 免费注册
发布采购

S2204TB 参数 Datasheet PDF下载

S2204TB图片预览
型号: S2204TB
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, 4-Trnsvr, CMOS, PBGA208, 23 X 23 MM, COMPACT, TBGA-208]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 33 页 / 339 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
 浏览型号S2204TB的Datasheet PDF文件第12页浏览型号S2204TB的Datasheet PDF文件第13页浏览型号S2204TB的Datasheet PDF文件第14页浏览型号S2204TB的Datasheet PDF文件第15页浏览型号S2204TB的Datasheet PDF文件第17页浏览型号S2204TB的Datasheet PDF文件第18页浏览型号S2204TB的Datasheet PDF文件第19页浏览型号S2204TB的Datasheet PDF文件第20页  
S2204  
QUAD GIGABIT ETHERNET DEVICE  
Table 8. Transmitter Output Signals  
Pin Name  
Level  
I/O  
Pin #  
Description  
TXAP  
TXAN  
Diff.  
LVPECL  
O
A17  
B17  
High speed serial outputs for Channel A.  
TXBP  
TXBN  
Diff.  
LVPECL  
O
O
O
O
C17  
D17  
High speed serial outputs for Channel B.  
High speed serial outputs for Channel C.  
High speed serial outputs for Channel D.  
TXCP  
TXCN  
Diff.  
LVPECL  
E17  
F16  
TXDP  
TXDN  
Diff.  
LVPECL  
F17  
G17  
TCLKO  
TTL  
J14  
TTL Output Clock at the Parallel data rate. This clock is provided  
for use by up-stream circuitry.  
Table 9. Mode Control Signals  
Pin Name  
Level  
I/O  
Pin #  
Description  
TESTMODE  
TTL  
I
E4  
Test Mode Control. Keep Low for normal operation.  
TESTMODE1  
TMODE  
TTL  
TTL  
I
I
D4  
Test Mode Control. Keep Low for normal operation.  
B13  
Transmit Mode Control. Controls the source of the clock used to  
input and output data to and from the S2204. When TMODE is  
Low, REFCLK is used to clock data on DINx[0:9] into the S2204.  
TBCA is used to clock parallel data DOUTx[0:9] out of the device.  
When TMODE is High, the TBCx inputs are used to clock data into  
their respective channels. The output clocks are derived from the  
receiver's CRUs.  
CLKSEL  
TTL  
I
C12  
REFCLK Select Input. This signal configures the PLL for the  
appropriate REFCLK frequency. When CLKSEL = 0, the REFCLK  
frequency equals the parallel word rate. When CLKSEL = 1, the  
REFCLK frequency is 1/2 the parallel data rate.  
REFCLK  
RESET  
RATE  
TTL  
TTL  
TTL  
I
I
I
H17  
C15  
D12  
Reference Clock is used for the transmit VCO and frequency  
check for the clock recovered from the receiver serial data. Also  
used to clock parallel data into the device when in REFCLK mode.  
When Low, the S2204 is held in reset. The receiver PLL is forced  
to lock to the REFCLK. The FIFOs are initialized on the rising edge  
of RESET. When High, the S2204 operates normally.  
When Low, the S2204 operates with the serial output rate equal  
to the VCO frequency. When High, the S2204 operates with the  
VCO internally divided by 2 for all functions.  
Note: All TTL inputs except REFCLK have internal pull-up networks.  
16  
October 9, 2000 / Revision E  
 复制成功!