S2054
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
Table 9. S2054 Performance Summary
Parameter
Operating Frequency *
Serial clock period
Byte clock period
Acquisition Time
S2054
Units
Mbit/s
ns
1250
.800
8.00
250
1062.5
.941
9.41
ns
250
ns
125.0
Reference clock
106.25
MHz
10
Word width
10
Bits
* ±10% lock range, nominal frequency is per FC-PH standard.
Table 10. S2054 Transmitter Timing
Parameters
Description
Min
Max
Units
Conditions
T
T
T
T
Data setup w.r.t. REFCLKP/N
1.5
—
ns
See note.
See note.
1
2
1
2
Data hold w.r.t. REFCLKP/N
Data setup w.r.t. TREFCLK
Data hold w.r.t. TREFCLK
Serial data rise and fall
1.0
1.5
1.0
—
—
—
ns
ns
ns
ps
—
T
,
T
300
20% to 80%, tested on a sample basis.
SDR
SDF
Transmitter Output Jitter Allocation
T
RMS
Serial data output random
jitter (RMS)
—
—
20
ps
ps
RMS, tested on a sample basis.
Measured with K28.7 pattern at
1250 Mbps.
J
T
Serial data output
deterministic jitter (p-p)
100
Peak-to-peak, tested on a sample basis.
Measured with K28.5 ± pattern at
1250 Mbps.
DJ
Note: All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output data levels
(.8V or 2.0V).
Table 11. S2054 Receiver Timing
Parameters
Description
Min
Max
Units
Conditions
T
3
RBC0 to RBC1 skew
7.5
8.5
ns
Tested on a sample basis.
T
4
Data setup w.r.t. RBC0, RBC1
Data hold w.r.t. RBC0, RBC1
Data setup w.r.t. RBC0, RBC1
Data hold w.r.t. RBC0, RBC1
RBC0, RBC1 rise and fall time
Data Output rise and fall time
Serial data input rise and fall
3.0
1.5
2.5
2.0
—
ns
ns
ns
ns
ns
ns
ps
µs
1.0625 GHz Mode
T
5
1.0625 GHz Mode
T
6
1.250 GHz Mode
T
7
1.250 GHz Mode
T
,
,
,
T
T
T
3.0
3.0
300
2.4
Measured from .8V to 2.0V.
Measured from .8V to 2.0V.
20% to 80%. (See Figure 10.)
RCR
RCF
DF
T
—
DR
T
—
SDR
T
SDF
Data acquisition lock time @
<1.0625Gb/s
—
LOCK
8B/10B IDLE pattern sample basis
Duty Cycle
RBC0/RBC1 Duty Cycle
40%
30%
60%
—
Input data eye opening
allocation at receiver input
for BER ≤1E–12
As specified in Fibre Channel FC–PH
standard eye diagram jitter mask.
Input Jitter
Tolerance
bit time
Note: Max. Load = 15 pF. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or
output data levels (.8V or 2.0V).
12
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
