GIGABIT ETHERNET CHIPSET
The parallel input data word can be either 10 bits or
20 bits wide, depending upon DWS pin selection. A
block diagram showing the basic chip function is
shown in Figure 3.
Parallel/Serial Conversion
The parallel-to-serial converter takes in 10-bit or 20-
bit wide data from the input latch and converts it to a
serial data stream. Parallel data is latched into the
transmitter on the positive going edge of REFCLK.
The data is then clocked synchronous to the clock
synthesis unit serial clock into the serial output shift
register. The shift register is clocked by the internally
generated bit clock which is 10 or 20 times the
REFCLK input frequency. The state of the serial out-
puts is controlled by the output enable pins, OE0 and
OE1. D[10] is transmitted first in 10-bit mode. D[0] is
transmitted first in 20-bit mode. Table 2 shows the
mapping of the parallel data to the 8B/10B codes.
10-Bit/20-Bit Mode
S2046/S2050
The S2046 operates with either 10-bit or 20-bit paral-
lel data inputs. Word width is selectable via the DWS
pin. In 10-bit mode, D[10-19] are used and D[0-9] are
ignored. See Table 2.
Reference Clock Input
The reference clock input (REFCLK) must be supplied
with a PECL single-ended AC coupled crystal clock
source with 100 PPM tolerance to assure that the trans-
mitted data meets the proposed 802.3z Specification
frequency limits. The internal serial clock is frequency
locked to the reference clock. Refer to Table 1 for
reference clock frequencies.
Table 1. Transmitter Operating Modes
Reference
Word
Clock
TCLK/TCLKN
Data Rate Width Frequency Frequency
DWS REFSEL (Mbps/sec) (Bits)
(MHz)
(MHz)
0
1
0
1
1250.0
1250.0
20
10
62.5
125.0
62.5
62.5
Table 2. Data Mapping to 8B/10B Alphabetic Representation
First Data Byte
TX[0:19] or
RX[0:19]
8B/10B alphabetic
representation
0
a
1
b
2
c
3
d
4
e
5
f
6
g
7
h
8
i
9
j
10 11
a
b
12
c
Second Data Byte
13 14 15 16 17
d
e
f
g
h
18
i
19
j
First bit transmitted in 20-bit mode
First bit transmitted in 10-bit mode
Figure 4. S2050 Functional Block Diagram
REFSEL
LOCKREFN
REFCLK
D
LOCKDETN
RX
RY
RLX
RLY
LPEN
SYNCEN
DWS
SHIFT
REGISTER
2:1
PLL CLOCK
RECOVERY
BITCLK
D
Q
20
D(0:19)
CONTROL
LOGIC
SYNC
DETECT
LOGIC
DIVIDER
SYNC
RCLK
RCLKN
March 29, 2000 / Revision B
3
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
