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S2050A-3/TD 参数 Datasheet PDF下载

S2050A-3/TD图片预览
型号: S2050A-3/TD
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, PQFP52, 10 X 10 MM, COMPACT, PLASTIC, QFP-52]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 19 页 / 158 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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®
DEVICE
SPECIFICATION
GIGABIT ETHERNET CHIPSET
GIGABIT ETHERNET CHIPSET
BiCMOS PECL CLOCK GENERATOR
GENERAL DESCRIPTION
S2046/S2050
S2046/S2050
FEATURES
• Functionally compliant with the 802.3z specification
• S2046 transmitter incorporates phase-locked
loop (PLL) providing clock synthesis from low-
speed reference
• S2050 receiver PLL configured for clock and
data recovery
• 1250 Mbps (Gigabit Ethernet) operation
• 10- or 20-bit parallel TTL compatible interface
• +3.3/+5V power supply
• Low-jitter serial PECL compatible interface
• Lock detect
• Local loopback
• Compact 52 PQFP package
• Gigabit Ethernet framing performed by receiver
• Continuous downstream clocking from receiver
• TTL compatible outputs possible with +5V I/O
power supply
The S2046 and S2050 transmitter and receiver pair
are designed to perform high-speed serial data trans-
mission over fiber optic or coaxial cable interfaces
conforming to the requirements of the proposed 802.3z
specification. The chipset is Gigabit Ethernet compli-
ant and supports 1250 Mbps with an associated 10
or 20-bit data word.
The chipset performs parallel-to-serial and serial-to-
parallel conversion and framing for block-encoded
data. The S2046 on-chip PLL synthesizes the high-
speed clock from a low-speed reference. The S2050
on-chip PLL synchronizes directly to incoming digital
signals, to receive the data stream. The transmitter
and receiver each support differential PECL-compat-
ible I/O for fiber optic component interfaces, to
minimize crosstalk and maximize data integrity. Local
loopback allows for system diagnostics. The I/O sec-
tion can operate from either a +3.3V or a +5V power
supply. (See
Ordering Information.)
Figure 1 shows a typical network configuration incor-
porating the chipset.
APPLICATIONS
High-speed data communications
• Ethernet backbone connections
• Mainframe
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes
Figure 1. System Block Diagram
Gigabit
Ethernet
Controller
S2046
TX
Optical
TX
Optical
RX
S2050
RX
S2050
RX
Optical
RX
Optical
TX
S2046
TX
Gigabit
Ethernet
Controller
March 29, 2000 / Revision B
1