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DEVICE SPECIFICATION
GIGABIT ETHERNET CHIPSET
GIGABIT ETHERNET CHIPSET
BiCMOS PECL CLOCK GENERATOR
GENERAL DESCRIPTION
S2046/S2047
S2046/S2047
FEATURES
• Functionally compliant with the IEEE 802.3z
Specification
• S2046 transmitter incorporates phase-locked
loop (PLL) providing clock synthesis from low-
speed reference
• S2047 receiver PLL configured for clock and
data recovery
• 1250 Mb/s (Gigabit Ethernet) operation
• 10-bit or 20-bit parallel TTL compatible
interface
• 1 watt typical power dissipation for chipset
• +3.3/+5 V power supply
• Low-jitter serial PECL compatible interface
• Lock detect
• Local loopback
• Compact 52 pin PQFP package
• Fibre Channel framing performed by receiver
• Continuous downstream clocking from receiver
• TTL compatible outputs possible with +5V I/O
power supply
The S2046 and S2047 transmitter and receiver pair
are designed to perform high-speed serial data trans-
mission over fiber optic or coaxial cable interfaces
conforming to the requirements of the IEEE 802.3z
specification. The chipset is Gigabit Ethernet compli-
ant and supports 1250 Mb/s with an associated 10 or
20-bit data word.
The chipset performs parallel-to-serial and serial-to-
parallel conversion and framing for block-encoded
data. The S2046 on-chip PLL synthesizes the high-
speed clock from a low-speed reference. The S2047
on-chip PLL synchronizes directly to incoming digital
signals, to receive the data stream. The transmitter
and receiver each support differential PECL-compat-
ible I/O for fiber optic component interfaces, to
minimize crosstalk and maximize data integrity. Local
loopback allows for system diagnostics. The I/O sec-
tion can operate from either a +3.3 V or a +5 V power
supply. With a 3.3 V power supply the chipset dissi-
pates only 1 W typically.
Figure 1 shows a typical network configuration incor-
porating the chipset.
APPLICATIONS
High-speed data communications
• Ethernet backbone connections
• Mainframe
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes
Figure 1. System Block Diagram
Gigabit
Ethernet
Controller
S2046
TX
Optical
TX
Optical
RX
S2047
RX
S2047
RX
Optical
RX
Optical
TX
S2046
TX
Gigabit
Ethernet
Controller
May 16, 2000 / Revision NC
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
