GIGABIT ETHERNET CHIPSET
Table 5. S2047 Pin Assignment and Descriptions
S2046/S2047
Pin Name
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LOCKDETN
Level
TTL
I/O
O
Pin #
45
43
42
40
38
37
35
34
32
31
29
28
25
24
22
21
18
17
15
14
52
Description
Outputs parallel data. The width of the parallel data bus is
selected by the state of the DWS pin. Parallel data on this bus is
clocked out on the falling edge of RCLK. In 20-bit mode, D[0] is
the first bit received. In 10-bit mode, D[10:19] are used and
D[0:9] are driven to the high state. In 10-bit mode, D[10] is the
first bit received.
TT L
O
Lock Detect. Active Low. When active, LOCKDETN indicates
that the PLL is locked to the incoming data stream. When
inactive, it provides a system flag indicating that the PLL is
locked to the local reference clock.
Loop Enable. Active High. When Active, LPEN selects the
loopback differential serial input pins (RLX, RLY). When inactive,
LPEN selects RX and RY (normal operation).
Data Width Select. Active High. The level on this pin selects the
parallel data bus width. When inactive, a 20-bit parallel bus
width is selected, and D[0:19] are active. When active, a 10-bit
parallel data bus is selected, D[10:19] are active and D[0:9] will
go active. (See Table 3.) A rising edge will reset the internal
counters (used for test).
Parallel data is clocked out on the falling edge of RCLK/RCLKN.
After a sync word is detected, the period of the current RCLK
and RCLKN is stretched to align with the word boundary. (See
Table 3 for frequency.)
(Externally capacitively coupled.) A free-running crystal-
controlled reference clock for the PLL clock multiplier. The
frequency of REFCLK is set by the REFSEL pin. (See Table 3.)
Synchronization (frame). Active High. Upon detection of a valid
sync symbol, this output goes active for one RCLK period. When
sync is active, the sync symbol is present on the parallel data
bus bits D[0:9] in 20-bit mode or D[0:9] and D[10:19] in 10-bit
mode.
(Externally capacitively coupled.) The serial loopback data
inputs. RLX is the positive input, and RLY is the negative input.
LPEN
TTL
I
8
DWS
Static
TTL
I
4
RCLK
RCLKN
Diff.
TTL
O
49
48
REFCLK
PECL
I
2
SYNC
TT L
O
51
RLX
RLY
Diff.
PECL
I
11
12
May 16, 2000 / Revision NC
9
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
