“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
Table 4. Pin Assignment and Descriptions (Continued)
Pin Name
Level I/O
Pin # Description
XDIN31
XDIN30
XDIN29
XDIN28
XDIN27
XDIN26
XDIN25
XDIN24
XDIN23
XDIN22
XDIN21
XDIN20
XDIN19
XDIN18
XDIN17
XDIN16
XDIN15
XDIN14
XDIN13
XDIN12
XDIN11
XDIN10
XDIN9
ECL
I
183
184
185
192
194
8
Expansion input data. Active High. These inputs are selected
by the most significant bit of the output configuration registers.
11
12
27
29
33
36
37
38
39
41
42
43
44
45
47
48
49
52
54
55
56
57
58
59
62
61
XDIN8
XDIN7
XDIN6
XDIN5
XDIN4
XDIN3
XDIN2
XDIN1
XDIN0
SDCLK
SDCLKN
ECL
I
70
69
Slave latch clock inputs (output data). True differential inputs.
Can be used single-ended with VBB1 and VBB2.
CNFGCLK
RESET
TTL
TTL
TTL
I
I
I
188
191
189
Address configuration clock. On rising edge, stores data into
output configuration register.
Chip reset. Active High. Asynchronously resets the register file.
CNFGSTB
Reconfiguration enable input. The contents of the register file
are parallel-loaded into the configuration latch when
CNFGSTB goes high, causing switch reconfiguration.
VBB1
VBB2
–
O
64
72
Reference threshold voltage outputs to allow provision for
single-ended capability for clock inputs.
6
June 15, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
