“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
Figure 2. Synchronous Mode
OPERATING MODES
t SUDI
tHDI
SYNCHRONOUS MODE
A
C
B
DINØ–31
In synchronous mode, two clock signals, MDCLK for
data input and SDCLK for data output, provide the latch
enable strobes to allow the input data and output data
to be stored in 32-bit latches. The S2024 is capable of
400-Mbit/s operation in this mode. The data is latched
on the falling edge of SDCLK and MDCLK.
MCMPWL
MCMPWH
MDCLK/N
SDCLK/N
t OVRL
Inputs MDCLK/MDCLKN and SDCLK/SDCLKN can be
used as true differentials or as single-ended clocking
signals. Onboard voltage reference outputs VBB1 and
VBB2 allow single-ended clocking capability when con-
figured as shown in Figure 8.
t SUXDI
t HXDI
A
B
XDINØ–31
DOUTØ–31
t SCKDO
A
B
TRANSPARENT MODE
In transparent, or asynchronous, mode, any data ap-
pearing at the input will be passed immediately through
to its designated output. Transparent transfer of data
through the latches takes place when both MDCLK and
SDCLK clock inputs are held high. In this mode the
S2024 is capable of up to a 800 Mbit/s NRZ data rate.
Figure 3. Transparent Mode
DIMPW
E
D
A
C
B
DINØ–31
tDIDO
B
tCFDO
RECONFIGURATION MODE
A
C
D
E
DOUTØ–31
CNFGSTB
XINØ–31
The S2024 can be selectively reconfigured one output
at a time, or any number of outputs can be reconfigured
simultaneously.Configurationdataisstoredin32registers,
one register for each output data pin. The 6-bit content
of each register selects the input data pin which is to be
connected to that output data pin. To connect an output
to a given input, the output to reconfigure is selected
usingOUTADD0–4andOAENtoenabletheappropriate
outputconfigurationregister. Withtheoutputconfigura-
tion register selected, the desired input pin connection
is provided on INADD0–5. The input pin selection on
INADD0–5 will be stored into the selected output con-
figuration register on the rising edge of CNFGCLK.
tXIDO
XIMPW
B
E
D
A
C
Figure 4. Reconfiguration Mode
t HOA
tSUOA
OUTADDØ–4
ADDRESS VALID
tSUOAE
When the switch is to be reconfigured, the S2024 mini-
mizes the time required through the use of an additional
configuration latch. While the switch is operational (and
prior to the time at which it must be reconfigured) a new
set of input addresses can be loaded into the register
file. Whenallregistershavebeenupdated, thecontents
oftheregistersareparallel-transferredtotheconfigura-
tion latch, when CNFGSTB goes high. This process
allows a switch reconfiguration in just 4 ns.
t HOAE
OAEN
INADDØ–5
CNFGCLK
tSUIA
t HIA
VALID
CCMPWH
CCMPWL
CSMPWH
t SUCFC
CNFGSTB
2
June 15, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
