HIPPI
S2020/S2021 SOURCE DEVICE STATE MACHINES
{REJ0-3} The REJect 0 through REJect 3 states are
entered at {REJ0} from either {IDLENAB} or
{REQCON} when the “CNRJ” decode is true.
These states are sequenced in order unless over-
ridden by a “DSBL” decode. The CON signal is
asserted on the HIPPI channel for these states,
providing the minimum four clock cycle response
for an active Connection Reject. This sequence is
exited to the {REJ4} state if “DSBL” remains false.
{WAITIDLE} The WAIT IDLE state is entered from the
{HANGERR} state if the “DSBL” decode remains
false. This state persists if either the “RQCN”,
“CNAC” or “CNRJ” decodes are true. This state is
exited to the {IDLENAB} state if the “IENB” decode
is true.
3.4 CONNECT SM EXTERNAL OUTPUTS
SRCAV SouRCe AVailable signal to the Destination
Host sytem. A “1” on this signal indicates that the
HIPPI channel, from the remote Source through the
local Destination device is available.
{REJ4-7} The REJect 4 through REJect 7 states are
entered at {REJ4} from {REJ3}. These states are
sequenced in order unless overridden by a “DSBL”
decode. The CON signal is deasserted for these
states, defining the active Connection Reject. This
sequence is exited to the {REJCOMPL} state if
“DSBL” remains false.
A “0” on this signal indicates that either the SDIC is
inactive, the Destination device is in a Reset or test
mode, or that the Data/FIFO SM is in an Error
state.
{REJCOMPL} The REJect COMPLete state is entered
from the {REJ7} state if “DSBL” decode is false, or
from the {CONNECTED} state if the “RQCN” de-
code is true. This state persists while “RQCN”.
“CNRJ” or “CNAC” are true. This state is exited to
the {IDLENAB} state if the “IENB” decode is true, or
to the {IDLDSAB} state if the “IDSB” decode is true.
CONRQ CONNect ReQuest signal to the Destination
Host system. A “1” on this signal indicates that the
REQ signal from the HIPPI channel has been as-
serted and recognized by the Destination device. A
“0” on this signal occurs when the REQ signal is
deasserted.
This signal when active indicates the time during
which the CONIN input may be used to actively
accept or reject a Connection Request.
{DISCON0-3}
The DISCONnect
0
through
DISCONnect 3 states are entered in sequence
from the {CONNECTED} state or from the
{INCOMPDCON} state when the “IENB” decode is
true. These states are sequenced in order unless
overridden by a “DSBL” decode.
CON CONnect signal to the HIPPI channel. The func-
tions of this signal are defined in the HIPPI-PH
spec.
4.0 S2021 HIPPI DATA/FIFO CONTROL
The function of this sequence is to assure that at
least four clock cycles of deasserted CON on the
HIPPI channel to recognize the Disconnected con-
dition of the channel. This sequence is exited to the
{IDLENAB} state if the “IENB” decode is true.
The HIPPI Destination device Host Data/FIFO State
Machine’ (SM) is part of the Host Data/FIFO Control
Block’. The State Machine controls the flow of data and
status from the HIPPI channel, through the S2021 Des-
tination device to the Destination Host FIFO and the
associated status registers.
{INCOMPDCON} The INCOMPlete DisCONnect state
is entered from the {CONNECTED} state if the
“IDSB” decode is true (REQ on the HIPPI channel
is deasserted, but CONIN remains asserted). This
state persists if the “IDSB” decoode remains true.
This state is exited to the {DISCON0} state if the
“IENB” decode is true, or to the {HANGERR} state
if either the “RQCN”, “CNAC” or “CNRJ” decodes
are true.
The Data/FIFO SM also provides addressing control to
vector data and status words to their appropriate regis-
ters.
The Host Data/FIFO SM has inputs from the HIPPI
channel and the Connect Control SM. Based on the
current set of inputs and the last state of this state
machine, the next Data/FIFO state is entered and a
related set of outputs is generated to the Destination
Host system.
{HANGERR} The HANG ERRor state is entered from
from either the {IDLDSAB} or {INCOMPDCON}
states if either the “RQCN”, “CNAC” or “CNRJ” de-
codes are true. These decodes represent errone-
ous sequences of the Host or channel control
signals. This state is exited after one clock cycle to
the {WAITIDLE} state.
As before, all external device signal names shall be
CAPITALIZED and underlined, the SM input ‘alphabet’
or decode names shall be in double quotes (“), and all
internal state names shall be enclosed in curly brackets
‘{}’. Signals internal to the Source device other than
previously defined state names shall be in caret brack-
ets ‘< >’.
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