Revision J – April 7, 2006
S2004 – Quad Serial Backplane Device
Data Sheet
Figure 4. Transmitter Block Diagram
RATE
REFCLK
TCLKO
REFCLK
DIN PLL
10x/20x
CLKSEL
CH_LOCK
TMODE
TMODE
8
8
DINA[0:7]
10
8B/10B
Encode
TXAP
TXAN
SYNC
DNA
Shift
Reg
KGENA
TXABP
0
1
2
3
TCLKA
8
8
DINB[0:7]
10
8B/10B
Encode
TXBP
TXBN
Shift
Reg
DNB
KGENB
TXBBP
0
1
2
3
TCLKB
8
8
10
DINC[0:7]
8B/10B
Encode
TXCP
TXCN
Shift
Reg
DNC
KGENC
TXCBP
0
1
2
3
TCLKC
8
8
DIND[0:7]
10
8B/10B
Encode
TXDP
TXDN
Shift
Reg
DND
KGEND
TXDBP
0
1
2
3
TCLKD
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