S2004 – Quad Serial Backplane Device
Revision J – April 7, 2006
Data Sheet
Figure 4. Transmitter Block Diagram
RATE
REFCLK
CLKSEL
CH_LOCK
TMODE
TMODE
8
DINA[0:7]
SYNC
DNA
KGENA
0 1
2
3
REFCLK
DIN PLL
10x/20x
TCLKO
8
8B/10B
Encode
10
Shift
Reg
TXAP
TXAN
TXABP
TCLKA
8
DINB[0:7]
8
8B/10B
Encode
10
Shift
Reg
TXBP
TXBN
TXBBP
DNB
KGENB
0 1
2
3
TCLKB
8
DINC[0:7]
DNC
KGENC
0 1
2
3
8
8B/10B
Encode
10
Shift
Reg
TXCP
TXCN
TXCBP
TCLKC
8
DIND[0:7]
DND
KGEND
0 1
2
3
8
8B/10B
Encode
10
Shift
Reg
TXDP
TXDN
TXDBP
TCLKD
AMCC Confidential and Proprietary
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