Revision J – April 7, 2006
S2004 – Quad Serial Backplane Device
Data Sheet
LIST OF FIGURES
Figure 1. Typical Quad Gigabit Ethernet Application ............................................................................................... 1
Figure 2. Typical Backplane Application .................................................................................................................. 5
Figure 3. S2004 Input/Output Diagram .................................................................................................................... 6
Figure 4. Transmitter Block Diagram ....................................................................................................................... 7
Figure 5. Receiver Block Diagram ........................................................................................................................... 8
Figure 6. DINx Data Clocking with TCLK ............................................................................................................... 10
Figure 7. DIN Clocking with REFCLK .................................................................................................................... 10
Figure 8. Channel Lock State Machine .................................................................................................................. 15
Figure 9. Channel Lock Synchronization Timing ................................................................................................... 16
Figure 10. External Receiver Clocking ................................................................................................................... 19
Figure 11. S2004 Diagnostic Loopback Operation ................................................................................................ 20
Figure 12. S2004 Pinout (Bottom View) ................................................................................................................. 30
Figure 13. S2004 Pinout (Top View) ...................................................................................................................... 31
Figure 14. Compact 23mm x 23mm 208 TBGA Package ...................................................................................... 32
Figure 15. S2004 – 208 PBGA Package Marking Drawing (Top View) ................................................................. 33
Figure 16. Transmitter Timing (Normal or Channel Lock Mode, TMODE = 0) ....................................................... 34
Figure 17. Transmitter Timing (Normal or Channel Lock Mode, TMODE = 1) ....................................................... 34
Figure 18. Receiver Timing (Full Clock Mode, CMODE = 1) ................................................................................. 35
Figure 19. Receiver Timing (Half Clock Mode, CMODE = 0, TMODE = 1) ............................................................ 36
Figure 20. Receiver Timing (External Clock Mode) (TCLKA to DATA Propagation Delay, TMODE = 0) .............. 36
Figure 21. TCLKO Timing ...................................................................................................................................... 36
Figure 22. Serial Input/Output Rise and Fall Time ................................................................................................. 39
Figure 23. TTL Input/Output Rise and Fall Time .................................................................................................... 39
Figure 24. Serial Output Load ................................................................................................................................ 39
Figure 25. High Speed Differential Inputs .............................................................................................................. 39
Figure 26. Receiver Input Eye Diagram Jitter Mask ............................................................................................... 39
Figure 27. Acquisition Time Eye Diagram .............................................................................................................. 39
Figure 28. Loop Filter Capacitor Connections ....................................................................................................... 40
AMCC Confidential and Proprietary
3
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
