Revision J – April 7, 2006
S2004 – Quad Serial Backplane Device
Data Sheet
Figure 13. S2004 Pinout (Top View)
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
DOUT
B7
DOUT
B6
DOUT
B2
DOUT
B0
DOUT
A7
DOUT
A4
DOUT
A1
TTLP
WR
TTLG
ND
DIG-
GND
DIG-
PWR
RCBP
RCBN
ERRC
EOFB
RCAN
RCAP
ERRB
ERRA
VDDA
RXAP
RXAN
VSS
1
2
DOUT
C1
KFLA
GB
DOUT
B4
DOUT
B3
DOUT
B1
DOUT
A5
DOUT
A3
DOUT
A0
TTLG
ND
DIG-
GND
CMOD
E
DIG-
PWR
EOFC
EOFA
DOUT
C4
DOUT
C0
DIG-
GND
KFLA
GC
TTLP
WR
DOUT
B5
TTLG
ND
DOUT
A6
DOUT
A2
KFL-
AGA
TTLG
ND
DIG-
PWR
DIG-
GND
GND
TRS
VDD
3
DOUT
C3
TTLG
ND
TTLG
ND
DIG-
GND
TTLG
ND
DIG-
PWR
TTLP
WR
TTLG
ND
TTLP
WR
TTLP
WR
DIG-
GND
CH_L
OCK
RCCN
RCCP
EOFD
SYNC
VSSA
NC
4
DOUT
C5
DOUT
C2
TTLP
WR
VSS-
SUB
RXBN
VDD
RXBP
VDDA
5
DOUT
C6
TTLG
ND
ERRD
VSS
NC
VDD
NC
6
DOUT
D1
KFLA
GD
DOUT
C7
TTLP
WR
VSS-
SUB
VSSA
VSSA
NC
7
DOUT
D2
DOUT
D0
TTLG
ND
TTLP
WR
VSS-
SUB
VDDA
NC
RXCP
RXCN
TMS
8
DOUT
D5
DOUT
D3
DOUT
D4
DIG-
PWR
VDD
TDI
9
DOUT
D6
DIG-
GND
RCDN
RCDP
DINA0
DINA4
DINA5
DINB0
DINB5
TCK
NC
VSS
10
11
12
13
14
15
16
17
DOUT
D7
DINA1
DINA6
DINA2
DINA7
DINB1
DINB6
VSSA
RATE
CAP1
RXDP
RXDN
VSS
TCLK
A
CLK-
SEL
VDD
TCLK
B
VSS-
SUB
TMOD
E
DINA3
VDDA
KGEN
A
TCLK
D
TCLK
O
LPEN
D
LPEN
B
LPEN
A
VSS-
SUB
DINB4
DINB7
DNB
DINC0
DINC2
DINC6
DNC
DINC5
DINC7
DIND1
DIND3
DIND4
DIND5
DIND6
NC
NC
NC
CAP2
VSS
VSSA
PWR
TXAN
TCLK
C
DIG-
GND
LPEN
C
PECL
PWR
PECL
PWR
RESE
T
DNA
DIND0
DIND2
DIND7
TC0
VDD
VDDA
TXAP
KGEN
B
PECL
GND
PECL
PWR
PECL
PWR
PECL
GND
DINB2
DINB3
DINC3
DND
TXCN
TXDP
NC
KGEN
C
KGEN
D
DIG-
PWR
REF-
CLK
DINC1
DINC4
TXDN
TXCP
TXBN
TXBP
Note: NC used as Test Pins. Do Not Connect.
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