QT2022/32 - Data Sheet: DS3051
Figure 23: MDIO Frame Structure
Device Management Interface - Address Frame Structure
MDC
MDIO Write
0
0
0
0
A4
A3
A0
R4
R3
R0
1
0
A15
A14
A1
A0
32 “1”s
Z
Idle Preamble
ST
Op Code
PHY Address
Register Address
Turnaround
Address
Idle
Write
Device Management Interface - Write Frame Structure
MDC
MDIO Write
0
0
0
1
A4
A3
A0
R4
R3
R0
1
0
D15
D14
D1
D0
32 “1”s
Z
Idle Preamble
ST
Op Code
PHY Address
Register Address
Turnaround
Data
Idle
Write
Device Management Interface - Read Increment Frame Structure
MDC
MDIO Read
Increment
0
0
1
0
A4
A3
A0
R4
R3
R0
0
D15
D14
D1
D0
32 “1”s
Z
Z
Idle
Idle Preamble
ST
Op Code
PHY Address
Register Address
Turnaround
Data
Read
Write
Device Management Interface - Read Frame Structure
MDC
MDIO Read
0
0
1
1
A4
A3
A0
R4
R3
R0
0
Z
D15
D14
D1
D0
32 “1”s
Z
Turnaround
Idle
Idle Preamble
ST
Op Code
PHY Address
Register Address
Data
Read
Write
9.6.1 Preamble Field (PRE)
At the beginning of each transaction the STA shall send a preamble sequence of 32 contiguous logic one bits on
MDIO with 32 corresponding cycles on MDC, to provide the QT2022/32 with a pattern that it can use to establish
synchronization. The QT2022/32 must observe this preamble sequence before it responds to any transaction.
9.6.2 Start Field (ST)
The Start of Frame is indicated by a <00> pattern.
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