QT2022/32 - Data Sheet: DS3051
9.4 MDIO Bus Initialization
The MDIO bus requires a valid LAN reference clock to be supplied to the EREFCLK input to initialize after powerup
or hard reset. The chip will not respond as expected to MDIO commands until a valid reference clock is present.
Once the MDIO bus has initialized, the reference clock supplied to EREFCLK can be removed and the MDIO bus
will continue to function normally. If the power is cycled or a hard reset is applied to the chip, the LAN reference
clock must be present to re-initialize the bus.
The MDIO bus does not require re-initialization after a soft reset (x.0.15 = 0).
9.5 MDIO Pin
The MDIO output has an open drain driver. An external pull resistor to 1.2V is expected as per Annex 45A of the
IEEE standard.
Figure 22: MDIO Open Drain Driver Configuration
1.2V
receive buffer
pullup, R
MDIO pin
external
capacitive loading
C
open drain
driver
COREGND
9.6 Management Frame Format
The QT2022/32 has an internal Address register which is used to store the address for MDIO reads and writes.
This MDIO Address register is set by sending an MDIO Address frame which specifies the register address to be
accessed within a particular logical device.
After an Address frame has been sent, the following Write, Read or a Post-Read-Increment-Address frame to the
same logical device accesses the register whose address is stored in the QT2022/32 MDIO Address register. An
Address frame should be followed immediately by the associated Write, Read or Post-Read-Increment-Address
frame.
Upon receiving a Post-Read-Increment-Address frame and having completed the read operation, the QT2022/32
shall increment the stored address in the MDIO Address register. If no Address frame is received before the next
Write, Read or Post-Read-Increment-Address frame, then the QT2022/32 shall use the incremented address cur-
rently stored in the Address register.
The Management Frame Format for Indirect Access is specified below.
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