QT2022/32 - Data Sheet: DS3051
Table 61: MDIO AC Parameters
Parameter
Description
Min
Typ
Max
300
Units
Conditions
Tdelay
delay from MDC rising edge to MDIO data
0
ns
RPU=400Ω;
Cload=470pF
output edge
See Note.
Fmax
MDC clock rate
3.125
MHz
ns
RPU=400Ω;
Cload=470pF
MDC high and low times
160
RPU=400Ω;
Cload=470pF
OPERATION UNDER LOW CAPACITIVE LOAD (1.2V pullup)
Tdelay
Fmax
delay from MDC rising edge to MDIO data
output edge
See Note.
0
32
ns
RPU=180Ω;
Cload=100pF
MDC clock rate
25.0
MHz
ns
RPU=180Ω;
Cload=100pF
MDC high and low times
20
RPU=180Ω;
Cload=100pF
Note: delay is measured from MDC rising edge Vih_min level (0.84V) to MDIO rising edge Vih_min level (0.84V) or MDIO falling edge
Vil_max level (0.36V)
Table 62: RDCC, RDCC_CLK, TDCC, TDCC_CLK AC Parameter Table
Parameter
Description
output clock frequency
Min
Typ
Max
Units
Conditions
fRDCC,
fTDCC
1.9375
MHz
tRDCC_delay
tTDCC_setup
tTDCC_hold
RDCC output data delay wrt RDCC_CLK
falling edge
0.1
μs
μs
μs
See Note 1.
TDCC input data setup time wrt
TDCC_CLK falling edge
0.1
See Note 2.
See Note 2.
TDCC input data hold time wrt
TDCC_CLK falling edge
0.1
Note 1: For an output rising edge, the delay is measured to a crossing level of 0.7*Vpullup. For an output falling edge, the delay is
measured to a crossing level of 0.3*Vpullup.
Note 2: Input timing is measured from the point where input signals cross a voltage level equal to COREVDD/2.
Table 63: EEPROM_SDA & EEPROM_SCL 3.3V Bidirectional Pad DC Parameters
Parameter
Description
output high voltage
Min
Typ
Max
Vpu
Units
Conditions
3.3V tolerant
Voh
Vol
Vih
Vil
V
output low voltage
0.2
V
sinking 3mA
input high voltage level
input low voltage level
input capacitance
0.84
V
0.4
5
V
Cin
pF
190
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