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QT2032 参数 Datasheet PDF下载

QT2032图片预览
型号: QT2032
PDF下载: 下载PDF文件 查看货源
内容描述: [10 Gb/s Serial-to-XAUI PHY ICs for Ethernet and Fibre Channel LAN/ SAN/WAN Applications (CDR)]
分类和应用: 局域网
文件页数/大小: 220 页 / 2383 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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QT2022/32 - Data Sheet: DS3051  
WIS Extended Alarms Status - Vendor Specific Register 2.C502h 1  
K1 Validated Byte Flag (RO/LH)  
Bit  
0
1
K2 Validated Byte Flag (RO/LH)  
2
Received Inconsistent K1 Bytes Flag (RO/LH)  
Received Inconsistent K2 Bytes Flag (RO/LH)  
S1 Validated Byte Flag (RO/LH)  
3
4
5
Reserved (RO)  
6
Received New J0 Trace Message Mismatch Flag (RO/LH)  
Received New J1 Trace Message Mismatch Flag (RO/LH)  
SD Alarm Flag (RO/LH)  
7
8
9
SD Timing Window Expired Flag (RO/LH)  
SF Alarm Flag (RO/LH)  
10  
11  
SF Timing Window Expired Flag (RO/LH)  
Reserved (RO)  
15:12  
1. The alarms in this register can be programmed to trip the LASI interrupt output signal. The mask register 2.C501h is used to control  
which alarms are enabled.  
Bit  
WIS OH Insert Enable - Vendor Specific Register 2.C600h  
0
Byte Insertion Enable 1 (RW)  
0 = Insertion Disabled (default)  
1 = Insertion Triggered  
15:1  
Reserved (RO)  
1. The “Insertion Enable” bit is used to trigger OH byte insertion when a fixed number of frame insertion events is selected. The number  
of insertion events is specified in Register 2.C601h-C603h, bits 15:14. If continuous insertion is specified, the “Insertion Enable” bit  
has no effect.  
Revision 5.11  
AppliedMicro - Confidential & Proprietary  
159  
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