QT2022/32 - Data Sheet: DS3051
WIS Extended Alarms Interrupt Control 1 - Vendor Specific Register 2.C501h
K1 Validated Byte Enable (RW)
Bit
0
1
2
3
4
0 = Disabled (default)
1 = Enabled
K2 Validated Byte Enable (RW)
0 = Disabled (default)
1 = Enabled
Received Inconsistent K1 Bytes Enable (RW)
0 = Disabled (default)
1 = Enabled
Received Inconsistent K2 Bytes Enable (RW)
0 = Disabled (default)
1 = Enabled
S1 Validated Byte Enable (RW)
0 = Disabled (default)
1 = Enabled
5
6
Reserved (RW)
Received New J0 Trace Message Mismatch Enable (RW)
0 = Disabled (default)
1 = Enabled
7
Received New J1 Trace Message Mismatch Enable (RW)
0 = Disabled (default)
1 = Enabled
8
SD Alarm Enable (RW)
0 = Disabled (default)
1 = Enabled
9
SD Timing Window Expired Enable (RW)
0 = Disabled (default)
1 = Enabled
10
11
SF Alarm Enable (RW)
0 = Disabled (default)
1 = Enabled
SF Timing Window Expired Enable (RW)
0 = Disabled (default)
1 = Enabled
15:12
Reserved (RO)
1. This is the alarm interrupt control for Register 2.C502h. It can be used to program which alarms will trip the LASI interrupt output sig-
nal.
158
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