QT2022/32 - Data Sheet: DS3051
Memory Select Register
1.C108h
Bit
2:0
BIST Select (RW)
0 = BIST 0, Memory 0 (default)
1 = BIST 1, Memory 0
2 = BIST 2, Memory 0
3 = BIST 2, Memory 1
4 = BIST 3, Memory 0
5 = BIST 3, Memory 1
6 = BIST 4, Memory 0
15:3
Reserved, RO
XFP Status Register
1.C200h
XFP Control Register
1.C201h
Bit
0
1
MOD_ABS Status, RO
MOD_DESEL Control, RW
0 = module selected, default
1 = module deselected
MOD_NR Status, RO
P_DOWN_RST Control, RW
0 = no power down, default
1 = power down
2
INT_B Status, RO
RX_LOS Status, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
3
14:4
15
TX_DIS Status, RO
Note: TX_DIS is an output pin of QT2022/32 driven by Reg-
ister 1.9.0
(same as TXENABLE)
136
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