QT2022/32 - Data Sheet: DS3051
Bit
PMA Vendor Specific 1.C001h
6
7
RXPLLOUT Enable, RW
0=RXPLLOUT disabled except in line timing mode (default)
1=RXPLLOUT enabled
LAN Reference Input Select
0 = use EREFCLK input (default)
1 = use TXPLLOUT input (disables TXPLLOUT output driver)
In conjunction with MDIO 1.C001h.3, this bit enables or disables the TXPLLOUT output driver. See Table 7 on page 35.
8
9
RXPLLOUT Output Frequency Select, RW
0 = 161MHz rxclk, Default
1 = test mode only. Do not use.
Force Line Timing Mode, RW
0 = Normal Operation (default)
1 = Force Line Timing Mode
This bit is used in conjunction with 1.C001h.14 to specify the current line timing state. See “Line Timing” on page 30. for more
information on line timing modes.
10
RXLOSB_I override, RW
0=no override, default
1=RXLOSB_I override
RXLOSB_I override does not impact MDIO register 1.10.0 functionality
11
12
Reserved, RO
PMA PLL VCO Center Frequency Override Enable (RW)
0 = No Override (default)
1 = Override
13
14
PMA PLL VCO Center Frequency Override Value (RW)
0 = Select LOW Frequency (default)
1 = Select HIGH Frequency
Note: Selection is active only when bit 1.C001h.12 is high.
Automatic Line Timing Mode Enable, RW
0 = Automatic Line Timing Mode disabled (default)
1 = Automatic Line Timing Mode enabled
This bit is used in conjunction with 1.C001h.9 to specify the current line timing state. For more information on line timing modes,
refer to section Section 6.2.2 on page 30.
15
PMA System Loopback Data Override, RW
1= Transmit Data
0= Transmit All 0s (default)
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