Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
PPC460EX Features
The following sections provide information on the features of the chip.
PowerPC 440 Processor
The PowerPC 440 processor (in 90nm technology) is designed for high-end applications: RAID controllers, SAN,
iSCSI, routers, switches, printers, set-top boxes, etc. It implements the Book E PowerPC embedded architecture
and uses the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture.
Features include:
• Up to 1.000GHz operation
• PowerPC Book E architecture
• 32KB I-cache, 32KB D-cache
– UTLB Word Wide parity on data and tag address parity with exception force
• Three logical regions in D-cache: locked, transient, normal
• D-cache full line flush capability
• 41-bit virtual address, 36-bit (64GB) physical address
• Superscalar, out-of-order execution
• 7-stage pipeline
• Three execution pipelines
• Dynamic branch prediction
• Memory management unit
– 64-entry, full associative, unified TLB with optional parity
– Separate instruction and data micro-TLBs
– Storage attributes for write-through, cache-inhibited, guarded, and big or little endian
• Debug facilities
– Multiple instruction and data range breakpoints
– Data value compare
– Single step, branch, and trap events
– Non-invasive real-time trace interface
• 24 DSP instructions
– Single cycle multiply and multiply-accumulate
– 32 x 32 integer multiply
– 16 x 16 -> 32-bit MAC
Floating Point Unit (FPU)
The chip has a built-in super scalar FPU that supports both single- and double-precision operations, and offers
single cycle through put on most instructions.
Features include:
• Five stages with 2 MFlops/MHz
• Hardware support for IEEE 754
• Single- and double-precision
• Single-cycle throughput on most instructions
• Thirty-two 64-bit floating point registers
AMCC Proprietary
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
