Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Document Revision History
Preliminary Data Sheet
Revision
1.23
Date
Description
Sept 21, 2006
Sept 12, 2006
Updated Recommended DC Operating Conditions table.
1.22
Updated Processor Clock values in Clocking Specifications table.
Updated Recommended DC Op Conditions and Signal Functional Description tables for PCI-X
DDR mode 2.
1.21
1.20
June 27, 2006
June 14, 2006
Updated signal lists. Corrected reference to PCIX0Cap in Signal Functional Description table.
Added reference to Note 6 for UART0_CTS register in Signal Functional Description table.
Fixed doc issue for PEROE signal in Signal Functional Description table. Fixed doc issue for
UARTSerClk signal throughout document. Fixed doc issue for PSRO1 signal in Signal Functional
Description table. Updated Clocking Specifications table and Serial Bootstrap ROM paragraph.
1.19
1.18
May 23, 2006
May 1, 2006
Updated ordering and PVR information, and core package graphic in Figure 3. Added RAID
acceleration section to Features, Description, and functional details sections.
1.17
1.16
April 6, 2006
Additional update to ordering and PVR information. GJG
March 8, 2006
Updated ordering and PVR information, part number list, and package diagram. GJG
Removed DMA statement from Serial Port feature statement. Removed reference to notes from
PERBLAST entry in signal functional description table. GJG
1.15
1.14
1.13
1.12
1.11
March 7, 2006
March 6, 2006
Updated description of On-Chip SRAM/L2 Cache in Introduction. GJG
Updated Signal Function Description table per JB, updated mailing address and copyright date in
disclaimer. GJG
January 9, 2006
November 15, 2005
October 26, 2005
Clarified information about DDR SDRAM I/O specifications. GJG
Corrected upper limit of allowable case temperature, documented reserved signal pins, added
bookmarks for signal lists. GJG
Restored multiplexed signal information to the “Signals Listed Alphabetically” table. Applied
corrections to the table from GB. GJG
1.10
October 17, 2005
1.09
1.08
1.07
1.06
July 12, 2005
May 23, 2005
May 20, 2005
Mar 10, 2005
Updated leakage current info, case temp range, DDR SDRAM Signal Termination graphic. GJG
Update Write timing diagrams. GJG
Updated system memory address map. Corrected functional block diagram. GJG
Removed text for unsupported COLA component. GJG
Removed references to unsupported COLA serial interface. Reformatted LOF, LOT to comply with
AMCC style. GJG
1.05
1.04
1.03
Feb 15, 2005
Dec 21, 2004
Dec 20, 2004
Update max case temp in Recommended DC Op Conditions table to match Ordering and PVR
Information table. GJG
Update Ordering and PVR info, PCI Express features info, DDR SDRAM read data path and read
cycle timing example, memory map. GJG
1.02
1.01
0.5
Sept 21, 2004
Sept 13, 2004
Sept 10, 2004
Aug 02, 2004
July 18, 2004
June 25, 2004
June 18, 2004
PCI-Express Rx Tx pin assignment changes. GJG
Converted to AMCC format, corrected tables, graphics as needed. GJG
Renamed 440SPe, added Mux table, VDDA 2.5V (IN PROGRESS)
Miscellaneous technical additions, PN and corrections from Support.
Correct TOC, LOF, LOT, broken cross-references.
Add alphabetic list, update Sys Mem address map.
Create initial data sheet.
0.4
0.3
0.2
0.1
78
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
