Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
DDR SDRAM Read Operation
Preliminary Data Sheet
The Read of the incoming Data from the SDRAM is done on the rising and falling edges of the differential DQS
signal. The Data must be centered to these edges for correct operation.
The PPC440SPe can delay with very fine granularity the DQS through the programming of the
MCIF0_RODC[RQFD] register field.
DDR SDRAM MemClkOut0 and Read Clock Delay
In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data
path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency.
The data are stored in the 8 Flip Flops of the Stage 1, such that it can be transferred later within a 8X period.
Figure 9. DDR SDRAM Read Data Path
FF: Flip-Flop
DDR 1X Clock
Ext FeedBack
Signals
Driver
MemDCFdbkD
FeedBack
Signal Gen
Coarse Delay
MCIF0_RFDC[RFFD]
Fine Delay
Read Start
Read Latency adjust circuit
CAS Lat Delay
DDR 1X Clock
Rec
Stage 2 Store
Oversampling
Fine Delay
MemDCFdbkR
DQS aligned
FBK signal
Cycles
Delay
+1
MCIF0_RFDC[RFOS]
Feedback
Data Capture
Window
T1 T2 T3 T4
MCIF0_RDCC[RDSS]
adjust
Oversampling
Clock
0
1
Q2_Ovs
7
Package
pins
Mux
0
2
4
6
FF
FF
Compare
FF
Q2
PLB bus
[0:63]
D
Read FIFO
Upper
(x64)
C
Mux
DQS Rising
Edge Sync
DQ
Data
(x64)
Stage 2
Stage 3
Stage 1
Lower
FF
FF
FF
1
3
5
Q3
PLB bus
[64:127]
FF
D
(x64)
7
C
Programmed
Read DQS
Delay
DQS Falling
Edge Sync
DQS
(Diff)
DDR 1X Clock
PLB 1X Clock
MCIF0_RQDC[RQFD]
74
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
