Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Preliminary Data Sheet
Table 2. DCR Address Map (4KB of Device Configuration Registers)
Function
Total DCR Address Space1
Start Address
End Address
Size
1KW (4KB)1
000
3FF
By function:
Reserved
000
00C
00E
010
012
014
020
030
040
060
080
090
0A0
0B2
0C0
0D0
0E0
0F0
100
120
140
160
168
180
200
00B
00D
00F
011
013
01F
02F
03F
05F
07F
08F
09F
0AF
0BF
0CF
0DF
0EF
0FF
11F
13F
15F
167
17F
1FF
3FF
12W
2W
Clocking Power On Reset
System DCRs
Memory Controller
External Bus Controller
Reserved
2W
2W
2W
12W
16W
16W
32W
32W
16W
16W
16W
14W
16W
16W
16W
16W
32W
32W
32W
8W
SRAM
L2 Controller
Memory Queue
I2O, DMA0 & DMA1
PLB
PLB to OPB Bridge Out
Reserved
Reserved
Interrupt Controller 0
Interrupt Controller 1
Interrupt Controller 2
Interrupt Controller 3
PCI-Express 0
PCI-Express 1
PCI-Express 2
Power Management
Reserved
24W
128W
512W
Ethernet MAL
Reserved
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a sin-
gle 32-bit (word) register. One KW (1024W) equals 4KB (4096 bytes).
8
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