Revision 1.23 - Sept 21, 2006
Preliminary Data Sheet
PPC440SPe Functional Block Diagram
Figure 2. PPC440SPe Functional Block Diagram
16 IRQs
Clock,
Control,
Reset
Timers
MMU
DCRs
Registers
MAC
DCR Bus
GP
Timers
GPIO
IIC
x2
UART
x3
Power
Mgmt
Universal
Interrupt
Controller
PPC440
Processor Core
JTAG
32KB
D-Cache
Trace
32KB
I-Cache
PCI-E
IRQ Handler
On-chip Peripheral Bus (OPB)
256 KB
L2 Cache/SRAM
OPB
Bridge
PLB
Arb
Ethernet
10/100/
1000
MII,
GMII
External
Bus Controller
(EBC)
Processor Local Bus (PLB)
Low Latency (LL) Segment
MAL
High Bandwidth (HB) Segment
I2O/DMA
Controller
(DMA0 and
DMA1)
Memory
Queue
DDR 1 and 2
SDRAM Cntl
64+8
XOR/DMA
Accelerator
Unit
(DMA2)
PCI-Express
PCI-E0 PCI-E1 PCI-E2
DDR PCI-X
64-bit
16
8 lanes 4 lanes 4 lanes
The PPC440SPe is a System on a Chip (SOC) designed around the IBM CoreConnect Bus™ Architecture.
Implemented with the Crossbar option, the CoreConnect buses provide:
• Two Master PLB bus 128-bit Data 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the
Read and Write data path (10.6 GB/s total)
• 32-bit OPB interfaces up to 83.33MHz for a maximum throughput of 333MB/s
AMCC Proprietary
5