Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Preliminary Data Sheet
PPC440SPe Functional Block Diagram
Figure 2. PPC440SPe Functional Block Diagram
16 IRQs
Clock,
Power
Mgmt
Control,
Reset
Universal
Interrupt
Controller
Timers
MMU
DCRs
Registers
MAC
UART
IIC
PPC440
Processor Core
GP
Timers
GPIO
DCR Bus
x2
x3
Trace
32KB
I-Cache
JTAG
On-chip Peripheral Bus (OPB)
32KB
D-Cache
PCI-E
IRQ Handler
OPB
Bridge
256 KB
L2 Cache/SRAM
PLB
Arb
Processor Local Bus (PLB)
Low Latency (LL) Segment
High Bandwidth (HB) Segment
Ethernet
10/100/
1000
External
Bus Controller
(EBC)
MAL
MII,
GMII
Memory
Queue
PCI-Express
PCI-E0 PCI-E1 PCI-E2
DDR PCI-X
64-bit
I2O/DMA
Controller
(DMA0 and
DMA1)
XOR/DMA
Accelerator
Unit
DDR 1 and 2
SDRAM Cntl
(DMA2)
64+8
8 lanes 4 lanes 4 lanes
16
The PPC440SPe is a System on a Chip (SOC) designed around the IBM CoreConnect Bus™ Architecture.
Implemented with the Crossbar option, the CoreConnect buses provide:
• Two Master PLB bus 128-bit Data 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the
Read and Write data path (10.6 GB/s total)
• 32-bit OPB interfaces up to 83.33MHz for a maximum throughput of 333MB/s
AMCC Proprietary
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
