Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Preliminary Data Sheet
Table 9. Recommended DC Operating Conditions (Sheet 3 of 3)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
V
Notes
V
Input Max Allowable Overshoot (3.3V LVTTL)
Input Max Allowable Undershoot (3.3V LVTTL)
Output Max Allowable Overshoot (3.3V LVTTL)
+3.9
IMAO
VIMAU
-0.6
V
V
+3.9
+95
V
OMAO
VOMAU3
TC
Output Max Allowable Undershoot (3.3V LVTTL)
-0.6
0
V
Case Temperature
°C
6
Notes:
1. PCI-X drivers meet PCI-X specifications.
2. SVREF = SVDD/2
3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the
PPC440SPe. See “Absolute Maximum Ratings” on page 58.
4. During chip power-up, OV
should begin to ramp before VDD. External voltage should not be applied to the chip I/O pins before
DD
is applied to the chip. A power-down cycle should complete (OV
OV
and VDD should both be below 0.4V) before a new power
DD
DD
up cycle is started.
5. LPDL is least positive down level; MPUL is most positive up level.
6. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board.
Table 10. Input Capacitance
Parameter
Group 1 (2.5V SSTL I/O)
Symbol
Maximum
Unit
Notes
C
5.7
pF
IN1
C
Group 2 (3.3V LVTTL I/O)
Group 3 (PCI-X I/O)
6.8
5.1
6.7
2.6
pF
pF
pF
pF
IN2
C
IN3
C
Group 4 (Receivers)
IN4
C
Group 5 (3.3V tolerant CMOS I/O)
IN5
AMCC Proprietary
61
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
