Revision 1.08 – October 15, 2007
440GRx – PPC440GRx Embedded Processor
Preliminary Data Sheet
Table 2. DCR Address Map
Function
Total DCR Address Space
1
By function:
Reserved
Clocking Power On Reset (CPR0)
System DCRs (SDR0)
Memory Controller (SDRAM0)
External Bus Controller (EBC0)
Reserved
PLB4-to-PLB3 Bridge Out
PLB3-to-PLB4 Bridge In
Reserved
PLB3 Arbiter
PLB4 Arbiter
PLB3-to-OPB0 Bridge
Reserved
Power Management
Reserved
Interrupt Controller 0
Interrupt Controller 1
Interrupt Controller 2
Power Management 1
Reserved
DMA-to-PLB3 Controller
Reserved
Ethernet MAL
Reserved
DMA-to-PLB4 Controller
Reserved
On Chip Memory (SRAM Controller)
Reserved
Notes:
1. DCR addresses are 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register. One
kiloword (1024W) equals 4KB (4096 B).
000
00C
00E
010
012
014
020
030
040
070
080
090
0A0
0B0
0B8
0C0
0D0
0E0
0F0
0F8
100
140
180
200
300
340
380
390
00B
00D
00F
011
013
01F
02F
03F
06F
07F
08F
09F
0AF
0B7
0BF
0CF
0DF
0EF
0F7
0FF
13F
17F
1FF
2FF
33F
37F
38F
3FF
16W
64W
128W
64W
16W
16W
16W
8W
8W
16W
16W
16W
16W
16W
2W
2W
2W
2W
Start Address
000
End Address
3FF
Size
1KW (4KB)
1
AMCC Proprietary
9
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
