440GRx – PPC440GRx Embedded Processor
Revision 1.08 – October 15, 2007
Preliminary Data Sheet
Block Diagram
Figure 2. PPC440GRx Functional Block Diagram
10
External
Interrupts
Clock
Control,
Reset
Timers
MMU
UIC
PPC440
Power
Mgmt
DCRs
83MHz max
- 30-bit addr
- 32/16-bit data
66MHz max
- 32 bits
- 6 devices
Processor
JTAG
32KB
D-Cache
Security
(optional)
Trace
32KB
I-Cache
SRAM
16KB
PLB (PLB4—128 bits)
DMA
Controller
DCR Bus
External
Peripheral
Controller
NAND
Flash
Controller
PCI
Bridge
PLB
Bridge
(X-bar)
PLB (PLB3—64 bits)
OPB
Bridge
DMA
Controller
GPT
DDR2/1
SDRAM
Controller
333MHz max
data rate
- 14-bit addr
- 64/32-bit data
Ethernet
10/100/1000
x2
ZMII
RGMII
On-chip Peripheral Bus (OPB 0)
MAL
GPIO
SPI
IIC
x2
BSC
UART
x4
The PPC440GRx is a system on a chip (SOC) using IBM CoreConnect Bus
™
Architecture.
6
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
