Revision 1.08 – October 15, 2007
440GRx – PPC440GRx Embedded Processor
Preliminary Data Sheet
Table 20. Peripheral Interface Clock Timings (continued)
Parameter
TmrClk frequency
Min
–
Max
Units
MHz
ns
Notes
100
TmrClk period
10
–
TmrClk high time
TmrClk low time
Notes:
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
ns
1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock
frequency is 83 MHz.
2. An internal PLL improves this duty cycle to a worst case of 48% minimum, 52% maximum.
Figure 6. Input Setup and Hold Waveform
Clock
1.25V(1.5V)
T
min
IS
T
min
IH
Inputs
Valid
Figure 7. Output Delay and Float Timing Waveform
Clock
1.25V(1.5V)
max
min
max
max
min
T
T
T
OV
OV
OV
T
T
min
T
OH
Outputs
OH
OH
High (Drive)
Float (High-Z)
Valid
Valid
Low (Drive)
74
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