Revision 1.08 – October 15, 2007
440GRx – PPC440GRx Embedded Processor
Preliminary Data Sheet
Table 19. Clocking Specifications
Symbol
Parameter
Min
Max
Units
Notes
SysClk Input
FC
TC
Frequency
33.33
66.66
30
MHz
ns
Period
15
TCS
TCH
TCL
Edge stability (cycle-to-cycle jitter)
–
±0.15
ns
High time
Low time
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
ns
Note: Input slew rate ≥ 1V/ns
PLL VCO
FC
TC
Frequency
Period
600
1333.33
1.66
MHz
ns
0.750
Processor (CPU) Clock
FC
TC
Frequency
Period
333.33
1.5
666.66
3
MHz
ns
1
MemClkOut and PLB Clock
FC
TC
Frequency
Period
133.33
166.66
7.5
MHz
ns
6
TCH
High time
45% of nominal period
55% of nominal period
ns
MAL Clock
FC
Frequency
Period
45
12
83.33
22.2
MHz
ns
TC
Notes:
1. The maximum supported processor clock frequency for any part is specified in the part number (see “Ordering and PVR Information” on
page 5).
Figure 5. Timing Waveform
1.7V (2.0V)
0.7V (0.8V)
T
T
CL
CH
T
C
Note: SysClk and GMCRefClk are 2.5V (3.3V tolerant). Slew rate should be measured between 0.7V and 1.7V.
AMCC Proprietary
71
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
