Revision 1.26 - June 16, 2008
PowerPC 440SPe Embedded Processor
Signal Description
Data Sheet
The PPC440SPe embedded controller is packaged in a 27mm Flip-Chip Plastic Ball Grid Array (FC-PBGA). The
following tables describe the package level pinout.
Table 5. Pin Summary
Group
No. of Pins
Total Signal Pins
AxVDD (1.5V)
495
3
AxVDD (2.5V HSS)
6
AxGND
5
OVDD (3.3V I/Os)
23
14
14
28
83
PxVDD (3.3/1.5V PCI)
SVDD (2.5/1.8V SDRAM)
V
DD (1.5V logic)
GND
Total Power Pins
Reserved
4
Total Pins
675
In the table “Signal Functional Description” on page 50, each I/O signal is listed along with a short description of its
function. Active-low signals (for example, RAS) are marked with an overline. See “Signals Listed Alphabetically” on
page 17 for the pin (ball) number to which each signal is assigned.
Multiplexed Signals
Some signals are multiplexed on the same pin so that the pin can be used for different functions. The signal names
shown in Table 6 on page 50 are not accompanied by signal names that might be multiplexed on the same pin. It is
expected that in any single application a particular pin will always be programmed to serve the same function. The
flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible.
Strapping Pins
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only
during reset and are used for other functions during normal operation (see “Strapping” on page 77). Note that
these are not multiplexed pins since the function of the pins is not programmable.
Multipurpose Signals
In addition to multiplexing, some pins are also multi-purpose. For example, the PCIX0Ack can function instead as
PCIX0ECC1 depending on the PCI interface mode of operation.
AMCC Proprietary
49
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
