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PPC440GX-3NF667C 参数 Datasheet PDF下载

PPC440GX-3NF667C图片预览
型号: PPC440GX-3NF667C
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 667MHz, CMOS, PBGA552, 25 X 25 MM, ROHS COMPLIANT, PLASTIC, FBGA-552]
分类和应用: 时钟外围集成电路
文件页数/大小: 92 页 / 571 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.21 – June 22, 2012  
PPC440GX Embedded Processor  
Initialization  
Data Sheet  
The PPC440GX provides the option for setting initial parameters based on default values or by reading them from  
a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered  
by strapping on external pins (see “Strapping” below).  
Strapping  
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default  
initial conditions prior to PPC440GX start-up. The actual capture instant is the nearest SysClk edge before the  
deassertion of reset. These pins must be strapped using external pull-up (logical 1) (recommended value is 3kΩ to  
3.3V) or pull-down (logical 0) (recommended value is 1 kΩ to GND) resistors to select the desired default  
conditions. They are used for strap functions only during reset. Following reset they are used for normal functions.  
The following table lists the strapping pins along with their functions and strapping options:  
Table 21. Strapping Pin Assignments  
Ball Strapping  
Function  
Option  
V24  
V02  
L07  
(UART0_DCD)  
(UART0_DSR)  
(GMC1TxEr)  
Serial device is disabled. Each of the four options (A–  
D) is a combination of boot source, boot-source width,  
and clock frequency specifications. Refer to the IIC  
Bootstrap Controller chapter in the PPC440GX  
Embedded Processor User’s Manual for details.  
A
B
0
0
0
1
1
1
0
x
1
0
0
1
0
1
0
0
1
1
C
D
Serial device is enabled. The option being selected is  
the IIC0 slave address that will respond with strapping  
data.  
0x54  
0x50  
Serial EEPROM  
During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device  
connected to the IIC0 port. At the de-assertion of SysReset, if the bootstrap controller is enabled, the PPC440GX  
sequentially reads 16 bytes from the ROM device on the IIC0 port and sets the SDR0_SDSTP0, SDR0_SDSTP1,  
SDR0_SDSTP2, and SDR0_SDSTP3 registers accordingly.  
The initialization settings and their default values are covered in detail in the PowerPC 440GX Embedded  
Processor User’s Manual.  
88  
AppliedMicro Proprietary