Revision 1.21 – June 22, 2012
PPC440GX Embedded Processor
Data Sheet
Table 19. I/O Timing—DDR SDRAM T and T
SD
HD
Notes:
1. TSD and THD are measured under worst case conditions.
2. The time values in the table include 1/4 of a cycle at the indicated clock speed.
3. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.5 ns from the values at 166MHz in the table
and add 1/4 of the cycle time for the lower clock frequency (e.g., TSD - 1.5 + 0.25TCYC).
TSD (ns)
THD (ns)
Clock Speed (MHz)
Signal Names
Reference Signal
DQS0
166
166
166
166
166
166
166
166
166
200
200
200
200
200
200
200
200
200
MemData00:07, DM0
MemData08:15, DM1
MemData16:23, DM2
MemData24:31, DM3
MemData32:39, DM4
MemData40:47, DM5
MemData48:55, DM6
MemData56:63, DM7
ECC0:7, DM8
1.240
1.236
1.223
1.221
1.238
1.286
1.234
1.257
1.237
0.916
1.018
1.017
0.951
1.030
1.014
0.994
0.994
1.000
1.224
1.188
1.224
1.185
1.230
1.175
1.214
1.154
1.243
0.542
0.522
0.527
0.532
0.533
0.536
0.534
0.546
0.532
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
MemData00:07, DM0
MemData08:15, DM1
MemData16:23, DM2
MemData24:31, DM3
MemData32:39, DM4
MemData40:47, DM5
MemData48:55, DM6
MemData56:63, DM7
ECC0:7, DM8
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
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