Revision 1.21 – June 22, 2012
PPC440GX Embedded Processor
Data Sheet
Table 18. I/O Timing—DDR SDRAM T , T , and T
SK SA
HA
Notes:
1. TSK is referenced to MemClkOut0(0). TSA and THA are referenced to MemClkOut0(90).
2. To obtain adjusted TSA values for lower clock frequencies, use 3/4 of the cycle time for the lower clock frequency and
subtract TSK maximum at 166MHz (0.75TCYC - TSKmax).
3. To obtain adjusted THA values for lower clock frequencies, use 1/4 of the cycle time for the lower clock frequency and add
TSK minimum at 166MHz (0.25TCYC + TSKmin).
TSK (ns)
TSA (ns)
THA (ns)
Clock Speed (MHz)
Signal Name
Minimum
0.184
Maximum
0.592
0.683
0.779
0.724
0.561
0.683
0.639
0.307
0.353
0.321
0.298
0.294
0.311
0.288
Minimum
3.908
3.817
3.721
3.776
3.939
3.817
3.816
3.443
3.397
3.429
3.452
3.456
3.439
3.462
Minimum
1.684
1.939
1.749
1.844
1.819
1.873
1.893
0.967
0.964
0.980
0.970
0.980
0.987
0.970
166
166
166
166
166
166
166
200
200
200
200
200
200
200
MemAddr00:12
BA0:1
0.439
BankSel0:3
ClkEn0:3
CAS
0.249
0.344
0.319
RAS
0.373
WE
0.393
MemAddr00:12
BA0:1
-0.283
-0.286
-0.270
-0.280
-0.270
-0.263
-0.280
BankSel0:3
ClkEn0:3
CAS
RAS
WE
80
AppliedMicro Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
