PPC440GX-3NF667C 参数 Datasheet PDF下载

Revision 1.21 – June 22, 2012

PPC440GX Embedded Processor

Data Sheet

Address Maps

The PPC440GX incorporates two address maps. The first is a fixed processor system memory address map. This

address map defines the possible contents of various address regions which the processor can access. The

second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running

on the PPC440GX processor through the use of

mtdcr

and

mfdcr

instructions.

Table 1. System Memory Address Map (Sheet 1 of 2)

Function

DDR SDRAM

SRAM

Local

Memory

1

Reserve

IMU

EBC

Reserved

UART0

Reserved

UART1

Reserved

IIC0

Reserved

IIC1

Reserved

OPB Arbiter

Reserved

Internal Peripherals

GPIO Controller

Ethernet PHY ZMII

Ethernet PHY GMII

Reserved

Ethernet 0 Controller

Ethernet 1 Controller

General Purpose Timer

TCPIP Accelerator 0

Ethernet 2 Controller

TCPIP Accelerator 1

Ethernet 3 Controller

Reserved

Expansion ROM

2

AppliedMicro Proprietary

1 4000 0700

1 4000 0780

1 4000 0790

1 4000 07A0

1 4000 0800

1 4000 0900

1 4000 0A00

1 4000 0B00

1 4000 0C00

1 4000 0D00

1 4000 0E00

1 4000 0F00

1 F000 0000

1 4000 077F

1 4000 078F

1 4000 079F

1 4000 07FF

1 4000 08FF

1 4000 09FF

1 4000 0AFF

1 4000 0BFF

1 4000 0CFF

1 4000 0DFF

1 4000 0EFF

1 EFFF FFFF

1 FFDF FFFF

254MB

7

256B

256B

256B

256B

256B

256B

256B

128B

16B

16B

0 8004 0000

0 FFFF 0000

1 0000 0000

1 4000 0000

1 4000 0200

1 4000 0208

1 4000 0300

1 4000 0308

1 4000 0400

1 4000 0420

1 4000 0500

1 4000 0520

1 4000 0600

1 4000 0640

0 FFFE FFFF

0 FFFF FFFF

1 3FFF FFFF

1 4000 01FF

1 4000 0207

1 4000 02FF

1 4000 0307

1 4000 03FF

1 4000 041F

1 4000 04FF

1 4000 051F

1 4000 05FF

1 4000 063F

1 4000 06FF

64B

32B

32B

8B

8B

64KB

1GB

Sub Function

Start Address

0 0000 0000

0 8000 0000

End Address

0 7FFF FFFF

0 8003 FFFF

Size

2GB

256KB