Revision 1.21 – June 22, 2012
PPC440GX Embedded Processor
Data Sheet
Internal Buses
The PowerPC 440GX features three IBM standard on-chip buses: the Processor Local Bus (PLB), the On-Chip
Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores
such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the PCI-X bridge connect to
the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR provides a lower bandwidth path for
passing status and control information between the processor core and the other on-chip cores.
Features include:
• PLB
- 128-bit implementation of the PLB architecture
- Separate and simultaneous read and write data paths
- 64-bit address
- Simultaneous control, address, and data phases
- Four levels of pipelining
- Byte enable capability supporting unaligned transfers
- 32- and 64-byte burst transfers
- 166MHz, maximum 5.2GB/s (simultaneous read and write)
- Processor:bus clock ratios of N:1 and N:2
• OPB
- Dynamic bus sizing 32-, 16-, and 8-bit data path
- 36-bit address
- 83.33MHz, maximum 333MB/s
• DCR
- 32-bit data path
- 10 bit address
On-Chip SRAM
Features include:
• Four banks of 64KB each for a total of 256KB
• Configurable as either Code (L2) cache or software-controlled on-chip memory, or SRAM
• Memory cycles supported:
- Single beat read and write, 1 to 16 bytes
- 32- and 64-byte burst transfers
- Guarded memory accesses
• Sustainable 2.6GB/s peak bandwidth at 166MHz
• Use as an L2 cache improves processor performance and reduces the PLB load
- Cache coherency maintained by a hardware snoop mechanism or software
- Data Array and Tag Array parity
- Unified data and instruction cache
- 4-way set associative
- 36-bit addressing
- Full LRU replacement algorithm
- Write through, look aside
• Use as Ethernet packet store allows Ethernet packets to be held for processing by the TAH unit
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
