Revision 1.15 – August 30, 2007
440GX – Power PC 440GX Embedded Processor
Data Sheet
Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
+1.4
Typical
+1.5
Maximum
+1.6
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Notes
VDD
Logic Supply Voltage (500MHz Rev A and 533MHz)
Logic Supply Voltage (667MHz and 800MHz)
I/O Supply Voltage
4
4
4
4
4
3
3
3
2
VDD
+1.5
+1.55
+3.3
+1.6
OVDD
SVDD
SVDD
AxVDD
AxVDD
SVREF
+3.0
+3.6
DDR SDRAM Supply Voltage (DDR clock up to 166MHz)
DDR SDRAM Supply Voltage (DDR clock = 200MHz)
PLL Supply Voltages (500MHz Rev A and 533MHz)
PLL Supply Voltage (667MHz and 800MHz)
DDR SDRAM Reference Voltage
+2.3
+2.5
+2.7
+2.5
+2.6
+2.7
+1.4
+1.5
+1.6
+1.5
+1.55
+1.25
+1.6
+1.15
SVREF+0.18
+1.35
SVDD+0.3
Input Logic High (2.5V SSTL)
Input Logic High (2.5V CMOS, 3.3V tolerant receiver)
Input Logic High (3.3V PCI-X)
1.7
VIH
0.5OVDD
OVDD+0.5
1
1
1
1
Input Logic High (3.3V LVTTL)
+2.0
-0.3
+3.6
SVREF-0.18
Input Logic Low (2.5V SSTL)
Input Logic Low (2.5V CMOS, 3.3V tolerant receiver)
Input Logic Low (3.3V PCI-X)
0.7
VIL
0.35OVDD
-0.5
0
Input Logic Low (3.3V LVTTL)
+0.8
SVDD
Output Logic High (2.5V SSTL)
+1.95
2.0
Output Logic High (2.5V CMOS, 3.3V tolerant receiver)
Output Logic High (3.3V PCI-X)
VOH
0.9OVDD
OVDD
OVDD
Output Logic High (3.3V LVTTL)
+2.4
0
V
V
V
V
V
Output Logic Low (2.5V SSTL)
0.55
0.4
Output Logic Low (2.5V CMOS, 3.3V tolerant receiver)
Output Logic Low (3.3V PCI-X)
VOL
0.1OVDD
Output Logic Low (3.3V LVTTL)
0
0
+0.4
0
IIL1
IIL2
Input Leakage Current (No pull-up or pull-down)
μA
μA
μA
V
Input Leakage Current for Pull-Down
0 (LPDL)
-150 (LPDL)
200 (MPUL)
0 (MPUL)
+3.9
5
5
IIL3
Input Leakage Current for Pull-Up
VIMAO
VIMAU
Input Max Allowable Overshoot (3.3V LVTTL)
Input Max Allowable Undershoot (3.3V LVTTL)
-0.6
V
AMCC
61
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
