Revision 1.15 – August 30, 2007
440GX – Power PC 440GX Embedded Processor
Data Sheet
I/O Timing—DDR SDRAM T
Notes:
DS
1. All of the DQS signals are referenced to MemClkOut0(0).
2. The TDS values in the table include 3/4 of a cycle at the indicated clock speed.
3. To obtain adjusted values for lower clock frequencies, subtract 4.5 ns from the 166MHz values in the table and add 3/4 of the
cycle time for the lower clock frequency (TDS - 4.5 + 0.75TCYC).
TDS (ns)
Clock Speed (MHz)
Signal Name
Minimum
4.902
4.872
4.842
4.855
4.832
4.867
4.825
4.880
4.826
3.660
3.672
3.664
3.660
3.671
3.666
3.666
3.658
3.662
Maximum
5.601
5.535
5.511
5.546
5.504
5.525
5.488
5.543
5.484
4.295
4.298
4.293
4.290
4.294
4.305
4.296
4.271
4.291
166
166
166
166
166
166
166
166
166
200
200
200
200
200
200
200
200
200
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
AMCC
81
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
