Revision 1.15 – August 30, 2007
440GX – Power PC 440GX Embedded Processor
Data Sheet
I/O Specifications—500MHz–800MHz
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.
Input (ns)
Output (ns)
Output Current (mA)
Setup
Time
(TIS min)
Signal
Clock
Notes
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
External Slave Peripheral Interface
PerData00:31
PerAddr00:31
PerPar0:3
2.8
2.9
2.7
1.8
na
1
1
6.6
6.6
6.0
5.1
5.8
5.5
5.5
5.7
na
0
0
15.3
15.3
15.3
15.3
15.3
15.3
15.3
15.3
na
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
na
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
1
0
PerWBE0:3
PerCS0:7
1
0
na
na
na
1
0
PerOE
na
0
PerWE
na
0
PerBLast
3.3
4.9
2.5
dc
na
na
na
na
0
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerReady[RcvrInh]
PerR/W
1
1
5.7
na
15.3
na
10.2
na
DMAReq0:3
DMAAck0:3
EOT0:3/TC0:3
dc
na
dc
na
6.0
6.3
5.1
6.8
dc
0
15.3
10.2
External Master Peripheral Interface
PerClk
na
na
na
na
1
na
6.7
na
na
0
15.3
15.3
na
10.2
10.2
na
PLB Clk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
1
ExtReset
HoldReq
HoldAck
ExtReq
ExtAck
2.8
na
na
0
na
1
5.5
na
15.3
na
10.2
na
1.5
na
na
0
na
na
1
5.7
5.7
na
15.3
15.3
15.3
10.2
10.2
10.2
BusReq
PerErr
na
0
2.5
na
AMCC
77
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
