Revision 1.15 – August 30, 2007
440GX – Power PC 440GX Embedded Processor
Data Sheet
DCR Address Map
4KB of Device Configuration Registers
Function
Total DCR Address Space
1
By function:
Reserved
Clocking Power On Reset
System DCRs
Memory Controller
External Bus Controller
External Bus Master I/F
PLB Performance Monitor
SRAM
L2 Controller
Reserved
PLB
PLB to OPB Bridge Out
Reserved
OPB to PLB Bridge In
Power Management
Reserved
Interrupt Controller 0
Interrupt Controller 1
Clock, Control, and Reset
Reserved
DMA Controller
Reserved
Ethernet MAL
Base Interrupt Controller
Interrupt Controller 2
Reserved
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit
(word) register. One kiloword (1024W) equals 4KB (4096 bytes).
000
00C
00E
010
012
014
016
020
030
040
080
090
0A0
0A8
0B0
0B8
0C0
0D0
0E0
0F0
100
140
180
200
210
220
00B
00D
00F
011
013
015
01F
02F
03F
07F
08F
09F
0A7
0AF
0B7
0BF
0CF
0DF
0EF
0FF
13F
17F
1FF
20F
21F
3FF
12W
2W
2W
2W
2W
2W
10W
16W
16W
64W
16W
16W
8W
8W
8W
8W
16W
16W
16W
16W
64W
64W
128W
16W
16W
480W
Start Address
000
End Address
3FF
Size
1KW (4KB)
1
AMCC
9
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
