Revision 1.15 – August 30, 2007
440GX – Power PC 440GX Embedded Processor
Data Sheet
I/O Specifications—All Speeds (Sheet 7 of 7)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz ± 100ppm.
4. The clock frequency for SMII operation is 125MHz ± 100ppm.
5. These are DDR signals that can change on both the positive and negative clock transitions.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
System Interface
SysClk
na
na
na
na
na
na
na
na
na
na
7.1
na
na
7.1
TmrClk
async
async
async
async
async
SysReset
Halt
na
na
na
na
SysErr
na
na
10.3
na
TestEn
na
na
na
na
DrvrInh2
na
GPIO00:31
Trace Interface
TrcClk
10.3
na
na
10.3
10.3
10.3
10.3
15.3
15.3
7.1
7.1
TrcBS0:2
TrcES0:4
7.1
TrcTS0:5 (GPIO set)
TrcTS1:5 (EBC set)
TrcTS6
7.1
10.2
10.2
76
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
