Revision 1.15 – August 30, 2007
440GX – Power PC 440GX Embedded Processor
Data Sheet
I/O Specifications—All Speeds (Sheet 4 of 7)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz ± 100ppm.
4. The clock frequency for SMII operation is 125MHz ± 100ppm.
5. These are DDR signals that can change on both the positive and negative clock transitions.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
Ethernet RGMII Interface
1,
async
GMC0RxClk
na
na
na
na
na
na
GMC0RxCtl
1
1
1
1
na
na
na
na
na
na
GMC0RxClk
GMC0RxClk
4, 5
4, 5
GMC0RxD0:3
5.1
6.8
1,
async
GMC0TxClk
na
na
na
na
5.1
6.8
GMC0TxCtl
na
na
na
na
0.5
0.5
3.5
3.5
5.1
5.1
6.8
6.8
GMC0TxClk
GMC0TxClk
4, 5
4, 5
GMC0TxD0:3
1,
async
GMC1RxClk
na
na
na
na
na
na
GMC1RxCtl
1
1
1
1
na
na
na
na
na
na
GMC1RxClk
GMC1RxClk
4, 5
4, 5
GMC1RxD0:3
5.1
6.8
1,
async
GMC1TxClk
na
na
na
na
5.1
6.8
GMC1TxCtl
na
na
na
na
na
na
0.5
0.5
na
3.5
3.5
na
5.1
5.1
na
6.8
6.8
na
GMC1TxClk
GMC1TxClk
4, 5
4, 5
GMC1TxD0:3
GMCRefClk
async
Ethernet TBI Interface
1,
async
TBIRxClk0
na
na
na
na
na
na
1,
async
TBIRxClk1
TBIRxD0:9
TBITxClk
na
2.5
na
na
na
1.5
na
na
na
na
na
6
na
na
na
1
na
5.1
na
na
6.8
na
TBIRxClkx
TBITxClk
1,
async
TBITxD0:9
5.1
6.8
AMCC
73
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
