Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Test Conditions
Output
Pin
Clock timing and switching characteristics are specified in accordance with operating
conditions shown in the table “Recommended DC Operating Conditions.” AC
50pF
C
specifications are characterized with V = 1.8V, T = rated temperature and a 50pF
DD
C
test load as shown in the figure to the right.
Clocking Specifications
Symbol
Parameter
Minimum
Maximum
Units
Notes
SysClk Input
FC
Frequency
Period
33.33
15
66.66
30
MHz
ns
TC
TCS
TCH
TCL
Edge stability (cycle-to-cycle jitter)
–
0.15
ns
High time
Low time
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
ns
Note:Input slew rate ≥ 1V/ns
PLL VCO
FC
TC
Frequency
Period
500
1
1000
2
MHz
ns
Processor Clock (CPU Clock)
FC
TC
Frequency
Period
–
2
500
–
MHz
ns
1
MemClkOut
FC
Frequency
Period
100
7.5
133.33
10
MHz
ns
TC
TCH
High time
35% of nominal period
65% of nominal period
ns
Notes:
1. The maximum supported processor clock frequency for any part is specified in the part number (see “Ordering and PVR Information”
on page 4).
Timing Waveform
2.0V
1.5V
0.8V
T
T
CL
CH
T
C
60
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
