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PPC440EPX-NTA667T 参数 Datasheet PDF下载

PPC440EPX-NTA667T图片预览
型号: PPC440EPX-NTA667T
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 677MHz, CMOS, PBGA680, 35 MM, PLASTIC, MS-034, BGA-680]
分类和应用: 时钟外围集成电路
文件页数/大小: 96 页 / 901 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.31 – February 16, 2012  
440EPx – PPC440EPx Embedded Processor  
Data Sheet  
Table 8. Signal Functional Description (Sheet 8 of 9)  
Notes:  
1. Receiver input has hysteresis  
2. Must pull up (recommended value is 3kΩ to OV  
(EOV  
for Ethernet)  
DD  
DD  
3. Must pull down (recommended value is 1kΩ)  
4. If not used, must pull up (recommended value is 3kΩ to OV  
(EOV  
for Ethernet)  
DD  
DD  
5. If not used, must pull down (recommended value is 1kΩ)  
6. Strapping input during reset; pull-up or pull-down required  
Signal Name  
System Interface  
Description  
I/O  
Type  
Notes  
3.3V tolerant  
2.5V CMOS  
SysClk  
Main system clock input.  
I
1
Set to 1 by an instruction machine check. The machine check is a  
result of the attempted execution of an instruction transferred on  
the PLB with a bus error. This output signal remains a logic 1  
until the machine check error is cleared in the Exception  
Syndrome Register (ESR).  
3.3V tolerant  
2.5V CMOS  
SysErr  
O
Main system reset. External logic can drive this bidirectional pin  
low (minimum of 16 cycles) to initiate a system reset. A system  
reset can also be initiated by software. Implemented as an open-  
drain output (two states; 0 or open circuit).  
3.3V tolerant  
2.5V CMOS  
SysReset  
I/O  
1, 2  
3.3V LVTTL  
Rcvr w/pull-up  
Halt  
Halt from external debugger.  
I
I
TmrClk  
Processor timer external input clock.  
3.3V LVTTL  
3.3V LVTTL  
GPIO00:15  
GPIO22:23  
General purpose I/O. To access these functions, software must  
set DCR register bits.  
I/O  
1
1
GPIO26:48  
GPIO16:21  
GPIO24:25  
General purpose I/O. To access these functions, software must  
set DCR register bits.  
3.3V tolerant  
2.5V CMOS  
I/O  
I/O  
General purpose I/O. To access these functions, software must  
set DCR register bits.  
3.3V tolerant  
2.5V CMOS  
GPIO49:63  
TestEn  
3.3V LVTTL  
Rcvr w/pull-  
down  
Test Enable.  
I
I
I
Note: Do not connect for normal operation.  
Receiver Inhibit. Active only when TestEn is active. Used for  
manufacturing test only.  
RcvrInh  
3.3V LVTTL  
1
1
3.3V tolerant  
2.5V CMOS  
Rcvr  
Mode Control. Active only when TestEn is active. Used for  
manufacturing test only.  
ModeCtrl  
LeakTest  
LeakTest2  
Leakage Test. Active only when TestEn is active. Used for  
manufacturing test only.  
3.3V LVTTL  
w/pull-up  
I
I
1
1
Reference Enable. Active only when TestEn is active. Used for  
manufacturing test only.  
RefEn  
3.3V LVTTL  
Driver Inhibit. Active only when TestEn is active. Used for  
manufacturing test only.  
3.3V LVTTL  
w/pull-up  
DrvrInh1:2  
TherMonA:B  
PSROOut  
I
1
On-chip PNP thermal monitor transistor.  
Thermal  
monitor  
I
5
A is the emitter and B is the base. The collector is grounded.  
Module characterization and screening. Use for test purposes  
only. Tie down as specified in Note 3 for normal operation.  
Perf screen ring  
oscillator  
O
1, 3  
64  
AppliedMicro Proprietary  
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