Revision 1.31 – February 16, 2012
440EPx – PPC440EPx Embedded Processor
Data Sheet
Table 8. Signal Functional Description (Sheet 6 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
(EOV
for Ethernet)
DD
DD
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to OV
(EOV
for Ethernet)
DD
DD
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
USB UTMI Peripheral Interface
USB2DI7:0
Description
I/O
Type
Notes
Unidirectional data inputs.
I/O
I/O
3.3V LVTTL
3.3V LVTTL
USB2DO7:0
Unidirectional data outputs.
Transmit data ready.
Receive active.
3.3V LVTTL
w/pull-down
USB2TxRdy
USB2RxAct
USB2RxDV
USB2RxErr
USB2LS0:1
I
I
3.3V LVTTL
3.3V LVTTL
w/pull-up
Receive valid.
I/O
I/O
I
1
1
Receive error.
3.3V LVTTL
3.3V LVTTL
w/pull-up
Line state 0 and Line state 1.
USB2TxVal
Transmit valid.
I/O
I/O
I/O
I/O
I/O
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
1
1
USB2Susp
Suspend.
USB2XcvrSel
USB2TermSel
USB2OM0:1
Transceiver select.
Termination select.
Operational mode.
USB 2.0 Clock (60MHz).
1
1
1
USB2Clk
1, 5
USB PHY Peripheral Interface
USB2Xcvr
USB2Xcvr
5V tolerant
Analog
USB 2.0 differential transceiver.
I/O
I/O
I/O
5
USB 2.0 external crystal (48MHz) or external oscillator (48MHz).
External crystal: In/Out differential must not be less than
500mV.
USB2XtalIn
USB2XtalOut
Analog
Analog
External oscillator: Connect oscillator with signal swing of 3.3V
between USB2XtalOut and ground.
See Table 18 on page 75.
External resistor connection for bias current.
USB2RExt
Use 3.4kΩ, 1% resistor connected to GND.
NAND Flash Interface
NFALE
Address Latch Enable.
O
O
3.3V LVTTL
3.3V LVTTL
1
1
NFCE0:3
Chip Enable (multiplexed with the PerCS0:3 signals).
Command Latch Enable.
NFCLE
O
I
3.3V LVTTL
3.3V LVTTL
1
1
Latches operational commands into the NAND Flash.
Ready/Busy.
NFRdyBusy
Indicates status of device during program erase or page read.
This signal is wire-OR connected from all NAND Flash devices.
Read Enable.
NFREn
NFWEn
O
O
3.3V LVTTL
3.3V LVTTL
1
1
Data is latched on the rising edge.
Write Enable.
Data is latched on the rising edge.
62
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