Revision 1.26 – October 15, 2007
440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
Figure 11. DDR SDRAM Write Cycle Timing
PLB Clk
MemClkOut
T
SA
Addr/Cmd
T
T
SK
DS
T
HA
T
DS
DQS
T
SD
T
SD
MemData
T
HD
T
HD
T
T
= Delay from falling edge of MemClkOut to rising/falling edge of signal (skew)
= Setup time for address and command
SK
SA
T
= Hold time for address and command signals from MemClkOut
HA
SD
HD
T
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
T
T
DS
Note: The timing data in the following tables is based on simulation runs using Einstimer.
Table 24. I/O Timing—DDR SDRAM T
DS
Notes:
1. All of the DQS signals are referenced to MemClkOut with the DQS delay line programmed to 1 cycle.
2. Clock speed is 166MHz.
TDS (ns)
Signal Name
Minimum
−0.030
−0.030
−0.050
−0.110
−0.140
−0.120
−0.060
−0.010
−0.140
Maximum
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
+0.650
+0.620
+0.580
+0.480
+0.410
+0.480
+0.580
+0.690
+0.420
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